The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
A patterned photoresist layer is commonly used to transfer a designed pattern having small feature sizes from a photomask to a wafer. The photoresist is light-sensitive and can be patterned by a photolithography process. Furthermore, the photoresist layer provides resistance to etch or ion implantation, which further requires a sufficient thickness. When IC technologies are continually progressing to smaller feature sizes, the thickness is not scaled down accordingly due to the resistance requirement. Depth of focus sufficiently enough to cover the thicker photoresist will degrade the imaging resolution. For example, a tri-layer resist is introduced to overcome the above challenge. However, due to various requirements, such as optical refractivity index and absorption, the tri-layer resist may be tuned to meet those requirements but does not have enough etch selectivity for patterning. Therefore, there is a need for a tri-layer resist material and a lithography method to address the above issue.